Engineer, Sr Staff IC Physical Design

The industry’s most respected fabless communications semiconductor, software and systems innovator, Broadcom, is looking for the world’s best and brightest engineers. As one of Fortune magazine’s “Most Admired Companies”, Broadcom promotes an open work environment, embracing change, taking risks and doing the impossible every day. Outstanding initiative and aggressive execution is at the core of who and what we are, and we take pride in outdoing, outsmarting and outselling the competition. With the fifth most valuable patent portfolio in the world and through the hard work and dedication of our people, Broadcom achieves a leadership position in every market we enter. With our culture of innovation rewarding brainpower and risk taking with industry-leading company ownership/benefits and competitive salary, this unique environment creates enormous opportunity for you.

Come leverage Broadcom's world-class talent and technology and make the impact in security SoC development you have always wanted to accomplish, with a team that you can count on. Join the team and be at your best at Broadcom.

Play a key role in physical design of Broadcom’s Security chips. Job function includes Synthesis, place-n-route, parasitic extraction, physical verification, timing optimization and analysis, electrical analysis including IR-drop, EM and coupling effect.

Work with analog IP, library group and package team to integrate mix-signal blocks and be able to leverage experience in circuit design.

Assess advanced process technology. Develop new methodology and flow to address deep sub-micron effects on 65nm and ensure seamless design tapeout.
Job Requirements :  Must have BSEE (MSEE is a plus) with 7+ years of relevent experience in physical design.

Must have strong technical strength covering RTL-synthesis to GDS tapeout. This includes hand-on experience in the areas of PnR, parasitic extraction, physical verification, timing analysis/optimization, padring design, IR/EM/coupling analysis.

Must have taped out chips using Magma(ICC/Astro) as PnR tool.

Must have experience in top-level/chip Floorplan and PnR (Magma/Astro/ICC) integration and timing closure.

Padring design experience for flipchip is a plus.

Must be able to program with Tcl and Perl languages.

Experience in logic synthesis, dataprep, DFT and RTL coding is a plus.

Should have good understanding of RTL coding, circuit design and process technology to interface with product design team and internal IP groups.

Must have good communication skills and be a team player.
City :  San Jose
State :  California
Country :  United States